The present invention relates to integrated circuit technology. More particularly, the present invention relates to configuration memory cells for user-configurable integrated circuits and to a hybrid configuration memory cell.
Static random-access memory (SRAM) cells are often used as configuration memory cells for a variety of user-programmable integrated circuits such as field programmable gate array (FPGA) integrated circuits. On chip powerup, the SRAM cells are loaded from a non-volatile memory array located either on the integrated circuit or off of the integrated circuit. This presents several problems.
A first problem is the time it takes to load the configuration memory from the non-volatile memory each time the circuit is powered up. Of course, this problem increases for large user-programmable integrated circuits. In addition, a significant amount of die area is consumed by on-chip non-volatile memory increases cost and yield issues. Furthermore, the fabrication process needs to be altered to fabricate on-chip non-volatile memory.
An alternative is to employ off-chip non-volatile memory to store the configuration code. One problem with this solution is that it creates opportunities for hackers to gain access to the configuration code.
Because of these and other reasons, it would be desirable to provide on-chip non-volatile memory storage for SRAM configuration cell code that does not require long configuration memory loading times, takes up only minimal additional die area, does not affect the complexity of the fabrication process. By providing the hybrid configuration memory cell, the present invention avoids the problems associated with off-chip configuration data storage. The various forms of on-chip PROM cells, including ReRAM and other devices have been shown to experience random failures due to a variety of mechanisms. By providing alternate ways to load the latch configuration memory cell of the present invention, the present invention also avoids the problems associated with on-chip non-volatile memory failures as detailed herein.
In addition, cross-coupled latch SRAM memory cells are susceptible to single event upset (SEU) events where a particle strike to a sensitive node can flip the state of the latch. Another aspect of the present invention provides a vertical resistor in one or both of the cross coupling paths of the latch in the SRAM cell to avoid the problem of SEU events to prevent transient particle strikes from changing the states of SRAM latches.